Browse Prior Art Database

Integrated Hardware Monitor

IP.com Disclosure Number: IPCOM000090227D
Original Publication Date: 1969-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Hosie, JA: AUTHOR

Abstract

The system monitor is integrated within a host computer and can be controlled dynamically under program control or manually. The bits which control monitor functions, along with a sample pulse, are transferred to interface status register 1. three-position switch is associated with each bit in register 1. In the normal position, data is entered from monitor instructions. The other two switch positions can be used to unconditionally set or reset the appropriate bit. Each time that register 1 is loaded, the data is also loaded into output buffer 2 for use in reduction of data.

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Integrated Hardware Monitor

The system monitor is integrated within a host computer and can be controlled dynamically under program control or manually. The bits which control monitor functions, along with a sample pulse, are transferred to interface status register 1. three-position switch is associated with each bit in register 1. In the normal position, data is entered from monitor instructions. The other two switch positions can be used to unconditionally set or reset the appropriate bit. Each time that register 1 is loaded, the data is also loaded into output buffer 2 for use in reduction of data.

The counter storage and controls comprise storage device S3 with associated adder 4. Monitor control clock 5 runs in a continuous cycle mode causing each counter and register of S3 to read out in turn to adder 4 and store back in the same S3 location. Each counter of S3 can be updated as often as once per machine cycle. Selective S3 counter reset can be performed by placing a reset bit and counter selection bit in register 1. This causes all zeros to be stored in the counter and register of S3. On an S3 counter overflow condition, the Of bit in adder 4 causes the address information contained in clock 5 and an Of bit to be transferred to output buffer 2. An S3 counter readout is accomplished by raising write buffer control 6 for a time equal to one pass of all counters. This need not be a synchronous operation since each counter has address identification.

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