Browse Prior Art Database

Amplifier

IP.com Disclosure Number: IPCOM000090248D
Original Publication Date: 1969-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Amrine, HE: AUTHOR [+2]

Abstract

The amplifier uses dual-gated FET's 1 and 2 which are connected in cascode to provide a relatively high G(m) at the input. The outputs FET's 1 and 2 are then fed to a second stage including transistor 3 followed by a fourth stage including transistor 4. A relatively low noise figure is achieved with high bandwidth by utilizing a current feedback 5 around the first three stages with a relatively high resistance. Feedback 5 is from the collector of transistor 4 in the third stage through a capacitor and two 50K ohm resistors 6 and 7 to the inputs FET's 1 and 2. Feedback 5 enables the input impedance to look like a low value. Feedback 5 is around three stages instead of one to thus enable the use of a relatively high feedback resistance so as to achieve a low noise figure.

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Amplifier

The amplifier uses dual-gated FET's 1 and 2 which are connected in cascode to provide a relatively high G(m) at the input. The outputs FET's 1 and 2 are then fed to a second stage including transistor 3 followed by a fourth stage including transistor 4. A relatively low noise figure is achieved with high bandwidth by utilizing a current feedback 5 around the first three stages with a relatively high resistance. Feedback 5 is from the collector of transistor 4 in the third stage through a capacitor and two 50K ohm resistors 6 and 7 to the inputs FET's 1 and 2. Feedback 5 enables the input impedance to look like a low value. Feedback 5 is around three stages instead of one to thus enable the use of a relatively high feedback resistance so as to achieve a low noise figure. Feedback loop 8 is from the emitter of transistor 4 back to FET's 1 and 2. This results in a reduction of the virtual input shunt capacitance of the amplifier.

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