Browse Prior Art Database

Variable Frequency Clock System

IP.com Disclosure Number: IPCOM000090250D
Original Publication Date: 1969-Mar-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Swan, EW: AUTHOR

Abstract

This clock system phase-locks very quickly to the data being read and remains on frequency subsequently in the absence of data for a predetermined period. Binary phase-modulated data and a reference signal from the data are transmitted to the input of differential low-pass filter 1.

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Variable Frequency Clock System

This clock system phase-locks very quickly to the data being read and remains on frequency subsequently in the absence of data for a predetermined period. Binary phase-modulated data and a reference signal from the data are transmitted to the input of differential low-pass filter 1.

The data signal always includes a transition in the middle of the data bit cell. This clock system removes the bit edge transition at the beginning and end of each bit and allows clock synchronization responsive to these mid-bit transitions. Low-pass filter 1 converts the single-ended data signal to a differential, 180 degree phase difference, signal at its output. Such signal is clipped in limit amplifier 2. The amplifier output signals A and B drive single-shots S-S 3 and 4. These respond to a negative transition of the signal. For every negative transition of signal A S-S 3 has an output. For every negative transition of signal B, S-S 4 has an output.

At the beginning of each new data signal input group, single-shot S-S 5 is fired for a preset time to suppress the bit edge signal being transmitted from S-S 4 by shutting off the And 6. Thus only the mid-bit signal from S-S 3 is transmitted to Or 7. The mid-bit signal is fed through And 8 to drive a 30 nanosecond single- shot S-S 9 which in turn drives clock 10.

The time of firing of S-S 5 is greater than the normal time of synchronizing clock 10. For the remainder of the data read time, it is desirabl...