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Checking of Check Circuitry

IP.com Disclosure Number: IPCOM000090336D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Baron, JM: AUTHOR [+2]

Abstract

A method of checking the operation of error-checking circuitry is provided. The system in which the checking circuitry is checked utilizes a modified odd-parity checking method. In the system, the lines are grouped and propagated from circuit card to circuit card with a parity bit. The parity for grouped lines is odd but with the polarities adjusted so that all 1's, +, is an illegal combination. If there are an even number of lines in the group, including parity, a legal combination is an odd number of 1's. A group with an odd number of lines legally must contain an even number of 1's. For example, legal and illegal combinations are shown for these three groups.

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Checking of Check Circuitry

A method of checking the operation of error-checking circuitry is provided.

The system in which the checking circuitry is checked utilizes a modified odd- parity checking method. In the system, the lines are grouped and propagated from circuit card to circuit card with a parity bit. The parity for grouped lines is odd but with the polarities adjusted so that all 1's, +, is an illegal combination. If there are an even number of lines in the group, including parity, a legal combination is an odd number of 1's. A group with an odd number of lines legally must contain an even number of 1's. For example, legal and illegal combinations are shown for these three groups. Group Legal Illegal +A + + +B - + +C + - +ABC Pty + - +D + - -E + + +DE Pty - - +F + - -F - -.

The drawing schematically shows the circuitry of a circuit card including the input and output checker circuitry 12 and 14. Although the drawing does not include the above groups, consideration of the modified odd parity system indicates that if any of the above groups of lines are energized by an operation pulse OP, all the outputs are forced + and output checkers 14 on the circuit card should all give a check indication OC. The normal set of output check latch 16 is degated by pulse OP and the combined check indication provides an alternate set of the latch circuit. Failure of latch 16 to set indicates an output checker failure. The input checkers 12 on all cards fed by the circuit...