Browse Prior Art Database

Error Retry Implementation

IP.com Disclosure Number: IPCOM000090343D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Leary, TG: AUTHOR

Abstract

With this circuit arrangement, the error routine mode is modified to permit retry in the error routine until a valid process cycle is guaranteed. In normal operation, a central processing unit CPU error line 10 is down. CPU status register 12 is conditioned for normal operating routines. Instruction address register 14, accumulator 16, and buffer register 18 are cooperating in normal manner with core storage 20. Error routine line 22 is down and error routine branchout circuitry 24 is inoperative. CPU interrupt latch 26 and error latch 28 are both down, the latter maintaining error lamp 30 dark.

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Error Retry Implementation

With this circuit arrangement, the error routine mode is modified to permit retry in the error routine until a valid process cycle is guaranteed. In normal operation, a central processing unit CPU error line 10 is down. CPU status register 12 is conditioned for normal operating routines. Instruction address register 14, accumulator 16, and buffer register 18 are cooperating in normal manner with core storage 20. Error routine line 22 is down and error routine branchout circuitry 24 is inoperative. CPU interrupt latch 26 and error latch 28 are both down, the latter maintaining error lamp 30 dark.

When an error occurs, line 10 is raised and normal processing is inhibited, but timing and other machine running lines remain active. On the first occurrence of an error, CPU status register gates 32 and 34 are conditioned permitting the error status to be set in register 12. At the same time, And 36 is conditioned for setting latch 28. Lamp 30 is now lighted and And 38 is conditioned for indicating and initiating the normal initial error remedial phase. The following operations occur. Error storage addresses are forced. The contents of register 14 and accumulator 16 are stored at forced address locations. During the storing process, the parity check error indication and signalling is blocked at terminal 40. A status bit is set into a predetermined position of register 12 if data in either register 14 or accumulator 16 is invalid.

If the last named processes are completed successfully, the remedial action proceeds as predetermined. Otherwise, the events are repeated. If a solid...