Browse Prior Art Database

Buffer Store Request

IP.com Disclosure Number: IPCOM000090344D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Boland, LJ: AUTHOR [+2]

Abstract

A data processing system has a storage hierarchy including main store MS implemented in magnetic cores and buffer store BS implemented in monolithic circuits. These stores are accessed by requests placed on core storage address bus CSAB and buffer storage address bus BSAB. Data is transferred into the stores over a storage bus in SB1 and from the stores over a store bus out SB0. SB0 is connected to SB1 to provide a path for writing data from MS into BS.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Buffer Store Request

A data processing system has a storage hierarchy including main store MS implemented in magnetic cores and buffer store BS implemented in monolithic circuits. These stores are accessed by requests placed on core storage address bus CSAB and buffer storage address bus BSAB. Data is transferred into the stores over a storage bus in SB1 and from the stores over a store bus out SB0. SB0 is connected to SB1 to provide a path for writing data from MS into BS.

MS is logically divided into Sets of blocks of words. BS is also divided into sets of blocks of words but BS is divided into four sectors so that a block of words within a given set can be written into any one of four different block locations in BS. To keep track of where the blocks of words are written, data directory DD is provided. When a block of words is initially written into BS, a block identifier is written into DD. Thus, in order to subsequently determine whether a particular word is within BS, DD is cycled so as to read the block ID's associated with a particular set therefrom. The block ID's are compared with the fetch request word address to determine if the block is in BS. If it is, a match signal is fed to address translator AT along with certain address bits from the request, to cause the appropriate word to be read from BS.

The storage hierarchy is accessed by requests from either a channel or from central processing element CPE. The latter requests are placed on BSAB and also in CPE request buffer CRB. For fetch requests, if the word is in BS, as determined in the manner previously described, a fetch request in CRB is cancelled. If, however, the word is not in BS, then CRB supplies a series of requests to CSAB to initiate the transfer of the block of words from MS to BS. Subsequently, when the words are placed on SB0 and...