Browse Prior Art Database

Deskewing System

IP.com Disclosure Number: IPCOM000090354D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Chase, FM: AUTHOR [+3]

Abstract

This system employs addressable memories 10 and 11, such as portions of a core memory, for the deskewing of data from a plurality of read stations 12 and 13. Each of the latter is coupled to a separate deserializer 14 or 15 which converts the serial data from the read station into parallel bytes of data. As each byte is converted, it is transferred in parallel to a corresponding input register 16 or 17 and then gated to the next available location in the corresponding memory 10 or 11. Write address counter 18 or 19 determines this next available location, address A, operates address decode circuitry 20 or 21 to direct the byte to that location, and transmits the address to the corresponding compare circuit 22 or 23.

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Deskewing System

This system employs addressable memories 10 and 11, such as portions of a core memory, for the deskewing of data from a plurality of read stations 12 and
13. Each of the latter is coupled to a separate deserializer 14 or 15 which converts the serial data from the read station into parallel bytes of data. As each byte is converted, it is transferred in parallel to a corresponding input register 16 or 17 and then gated to the next available location in the corresponding memory 10 or 11. Write address counter 18 or 19 determines this next available location, address A, operates address decode circuitry 20 or 21 to direct the byte to that location, and transmits the address to the corresponding compare circuit 22 or
23.

Read address counter 24 indicates the address in both memories of the last bytes of data read from them, address B, and supplies this address to the compare circuits. The latter each compare the respective A1 or A2 and B inputs. If the A address is greater than the B address, indicating that data is ready for transmission, the compare circuit supplies an output to And 25. If the A address exceeds the B address by a specific number X, over-skew is indicated and the compare circuit supplies an output to Or 26. An output from Or 26 thus indicates trouble in the system resulting in over-skew.

When both compare circuits supply outputs to And 25, the latter supplies a Data Ready signal to the receiving unit. The receiver then requests a sim...