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Browse Prior Art Database

Identifying Pluggable Unit on Parity Errors

IP.com Disclosure Number: IPCOM000090355D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Leary, TG: AUTHOR

Abstract

The identification of a fault in or between a particular pluggable unit of origination register 12 or of destination register 14 between which data is transferred is afforded by circuitry coupled to associated parity checking circuits 16 and 18.

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Identifying Pluggable Unit on Parity Errors

The identification of a fault in or between a particular pluggable unit of origination register 12 or of destination register 14 between which data is transferred is afforded by circuitry coupled to associated parity checking circuits 16 and 18.

And's 20...27 are coupled to circuits 16 and 18. Even-numbered And's 20, 22, 24, and 26 are connected to circuits 16. Odd-numbered And's 21, 23, 25, and are connected to circuits 18. And's 28 and 29 are coupled to parity bit lines 32 and 34 respectively. Control line 36 for sampling register 12 is connected to all even-numbered And's. Control line 38 is connected to all odd-numbered And's. Not-error line 39 is connected to all And's 20...29. The even-numbered And's are used to set flip-flops 41...45. The odd-numbered And's are used to reset the same flip-flops. Flip-flop reset line 47 is connected to reset all flip-flops
41...45. Lamps 51...55 are individually connected to flip-flops 41...45 With this arrangement, the transfer of data from register 12 to register 14 results in the setting and then resetting of each flip-flop provided the pluggable units are in good condition. If they are not, the flip-flop corresponding to a part of the register having at least one faulty order is indicated by the associated lamp glowing. Or 57 and And 58 to which the outputs of Or 57 and a test line 59 are applied indicates on line 60 that an error has occurred in transferring data. Further And...