Browse Prior Art Database

Overlapped Read and Write Cycle Storage

IP.com Disclosure Number: IPCOM000090358D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Day, RC: AUTHOR

Abstract

This is a coincident current magnetic element storage subsystem which permits overlapping of read and write operations. The Fetch-Store OP signal is transmitted from the central processing unit CPU to the memory subsystem and is stored in operation register 10. The previous operation code is stored in register 12. A comparison is made with the previous operation code to sense the case in which a single storage element is being operated on in two subsequent cycles. Operation decoder 14 is indicates which of the four possible sequences of read following read RR, write following read RW, write following write WW and read following write WR is called for by the current operation code. The Fetch-Store Address is read into read storage address register 16 from the CPU.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 2

Overlapped Read and Write Cycle Storage

This is a coincident current magnetic element storage subsystem which permits overlapping of read and write operations. The Fetch-Store OP signal is transmitted from the central processing unit CPU to the memory subsystem and is stored in operation register 10. The previous operation code is stored in register 12. A comparison is made with the previous operation code to sense the case in which a single storage element is being operated on in two subsequent cycles. Operation decoder 14 is indicates which of the four possible sequences of read following read RR, write following read RW, write following write WW and read following write WR is called for by the current operation code. The Fetch- Store Address is read into read storage address register 16 from the CPU. This address is compared by comparer 18 with write storage address register 20, loaded in the previous cycle.

This comparison is used to determine the common logical select lines as well as common physical select lines as indicated on the output lines to decode and control 22. Decode 22 generates the proper control signals to control driver and gate switching and bit entry. Data from the CPU for use in a store operation is coupled to store register 24. This data is transferred to storage data register 26 and, through bit entry 28, is stored in storage matrix 30 in the write portion of the cycle. Matrix 30 comprises conventional array of storage elements with the e...