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Dual Emitter Avalanche Transistor Memory Array

IP.com Disclosure Number: IPCOM000090360D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Davidson, EE: AUTHOR

Abstract

The open base avalanche characteristics of a transistor can be used as a storage element in a memory array. Line 10 is the open base characteristic of a transistor over both the linear and avalanche regions of operation of the transistor. If this transistor is biased by the load line 1/R the transistor has two stable operating states. Therefore a transistor so biased can be used as the memory cell in an array. To write information into any transistor T2 the data stored in such transistor must first be erased by putting transistor T2 into the 0 state.

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Dual Emitter Avalanche Transistor Memory Array

The open base avalanche characteristics of a transistor can be used as a storage element in a memory array. Line 10 is the open base characteristic of a transistor over both the linear and avalanche regions of operation of the transistor. If this transistor is biased by the load line 1/R the transistor has two stable operating states. Therefore a transistor so biased can be used as the memory cell in an array. To write information into any transistor T2 the data stored in such transistor must first be erased by putting transistor T2 into the 0 state.

This is accomplished by raising the potential of word line 12 to V1, while the potential on data line 14 is maintained at V3 so that absolute value V3-VL< Vsus. Simultaneously, the potential on the bit line is raised to V5 so that absolute value V3-V5< Vsus. Transistor T2 is then is 0 state. If this is the desired state then the potential on the word line 12 is returned to V0. The potential on the bit line 14 is returned to zero while the data line 16 is maintained at V3. However, if transistor T2 is to be placed in the 1 state, then word line 12 is pulsed negative and data line 14 is pulsed positive so that absolute value V4-V2 > BVceo causing transistor T1 to switch to the 1 state.

To read the state of transistor T2, word line 12 is pulsed above the voltage on the bit line 16 so that emitter e1 turns off and emitter number e2 turns on. The output voltage E is developed...