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# Functional Logic Checker

IP.com Disclosure Number: IPCOM000090365D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 30K

IBM

## Related People

DuBois, TF: AUTHOR

## Abstract

Functional logic 10, containing both combinatorial and sequential chains, can be error-checked by considering the outputs of the functional logic circuits as a group of 1's and 0's at a particular instant in time. The number of 1's can be counted in HEX decoder 12 to produce a digital output identified as a HEX number which is actually a digital representation of the number of 1's in the output from functional logic 10. The HEX number is fed to one side of comparator 14. The other side of comparator 14 is obtained from a set of latches 16 which represent a different HEX digit formed as a result of selected input conditions to functional logic 10. This second input to comparator 14 is the complement of the HEX digit formed at HEX decoder 12.

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Functional Logic Checker

Functional logic 10, containing both combinatorial and sequential chains, can be error-checked by considering the outputs of the functional logic circuits as a group of 1's and 0's at a particular instant in time. The number of 1's can be counted in HEX decoder 12 to produce a digital output identified as a HEX number which is actually a digital representation of the number of 1's in the output from functional logic 10. The HEX number is fed to one side of comparator 14. The other side of comparator 14 is obtained from a set of latches 16 which represent a different HEX digit formed as a result of selected input conditions to functional logic 10. This second input to comparator 14 is the complement of the HEX digit formed at HEX decoder 12. The timing for the operation is derived from the input timing pulses or can be obtained from remote clocking. The output of comparator 14 is sampled at appropriate times into a check latch circuit 18 which indicates the existence of the desired comparison and accordingly produces a check output. The circuitry can be changed to operate on 0's rather than 1's. The arrangement is independent of the functional logic arrangement and is capable of detecting multiple errors.

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