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Address Register and Compare Circuit Checking

IP.com Disclosure Number: IPCOM000090407D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Blunk, VL: AUTHOR [+4]

Abstract

The proper functioning of a set of registers and associated Exclusive-Or compare circuits can be checked during the operation of a data processing system. The circuitry is a portion of a system having a high-speed, low-capacity buffer which retains the most recently accessed data from a larger-capacity, slow-speed memory. Address Registers 1...16 retain main storage address of sixteen blocks of data presently residing in sixteen sections of the high-speed buffer. Whenever the data processing system addresses main storage, the block addressing residing in sixteen sections of the high-speed buffer. Whenever the data processing system addresses main storage, the block addressing portion of the address information on the Address Bus is compared with the contents of each of the Address Registers 1...16.

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Address Register and Compare Circuit Checking

The proper functioning of a set of registers and associated Exclusive-Or compare circuits can be checked during the operation of a data processing system. The circuitry is a portion of a system having a high-speed, low-capacity buffer which retains the most recently accessed data from a larger-capacity, slow-speed memory. Address Registers 1...16 retain main storage address of sixteen blocks of data presently residing in sixteen sections of the high-speed buffer. Whenever the data processing system addresses main storage, the block addressing residing in sixteen sections of the high-speed buffer. Whenever the data processing system addresses main storage, the block addressing portion of the address information on the Address Bus is compared with the contents of each of the Address Registers 1...16. An output from one of Compare circuits
1...16 indicates that the addressed data is in the high-speed buffer. The output from a particular Compare circuit is entered into a Compare Encoder utilized to address the proper section of the high-speed buffer.

Logic which indicates that there is no-compare of the address information with that retained in the Address Registers 1...16 causes access to be made to main storage for the data. Further, a replacement algorithm is then interrogated to indicate a particular one of the sections in the high-speed buffer to be replaced. Based on this determination, the address information on the Address Bus is gated into the Address Register associated with the replaced section.

All of the previously mentioned apparatus enters into the normal functioning of the data processing system. By providing an additional series of trig...