Browse Prior Art Database

Multiple Compare Check

IP.com Disclosure Number: IPCOM000090408D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Blunk, VL: AUTHOR [+3]

Abstract

The article entitled "Address Register and Compare Circuit Checking" on page 1500 of this issue describes one check which must be made in a data processing system having a small-capacity, high-speed buffer for retaining a portion of the data accessed from a high-capacity, low-speed memory. One additional check which must be performed, shown in the drawing, is to insure that only one compare is detected on any particular cycle where a compare is made. The size of the low-capacity, high-speed buffer can be varied from system to system. The multiple compare check can be made with a high-speed buffer size which requires from two to four groups of eight address registers.

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Multiple Compare Check

The article entitled "Address Register and Compare Circuit Checking" on page 1500 of this issue describes one check which must be made in a data processing system having a small-capacity, high-speed buffer for retaining a portion of the data accessed from a high-capacity, low-speed memory. One additional check which must be performed, shown in the drawing, is to insure that only one compare is detected on any particular cycle where a compare is made. The size of the low-capacity, high-speed buffer can be varied from system to system. The multiple compare check can be made with a high-speed buffer size which requires from two to four groups of eight address registers.

The logic of circuit A is placed on a single circuit card and is capable of detecting the existence of only one compare for a group of eight registers shown in the above mentioned article. One of these circuit cards is used for each group of eight registers provided in a particular high-speed buffer design capacity.

The logic of circuit B is placed on a second circuit card and brings together the outputs from the 2, 3 or 4 cards containing circuit A. The group of And's, noted generally at 1, is used to detect a multiple compare situation for any one group of eight registers. This is an error condition signalled through Or 2. The fact of at least one compare per eight registers is checked with the other groups of eight registers for more than one group compare in the remainder o...