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Pulse Train Monitoring Circuit

IP.com Disclosure Number: IPCOM000090414D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

McDowell, AW: AUTHOR

Abstract

This circuit provides an output which rises upon the occurrence of an initial pulse of a train and stays in that condition so long as the pulses are recurrent at a predetermined frequency. The output falls at the time of a missing pulse in the train or when the frequency of the train shifts beyond a tolerance. The circuit can be used as a missing pulse detector, in various phase comparison circuits, in frequency drift detector circuits, motion monitoring devices such as speed controllers, or anywhere in which it is required to check the predicted regularity of a pulse train.

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Pulse Train Monitoring Circuit

This circuit provides an output which rises upon the occurrence of an initial pulse of a train and stays in that condition so long as the pulses are recurrent at a predetermined frequency. The output falls at the time of a missing pulse in the train or when the frequency of the train shifts beyond a tolerance. The circuit can be used as a missing pulse detector, in various phase comparison circuits, in frequency drift detector circuits, motion monitoring devices such as speed controllers, or anywhere in which it is required to check the predicted regularity of a pulse train.

The input pulses A to be monitored are each of duration T and are recurrent at period F. These pulses can be of a regular shape as shown, or they may be of spike or other less ideal shape. For example, when the circuit is used in a phase-null detector arrangement, pulses A can be poorly shaped at the beginning and end of the train. For this reason an arrangement including negative Or 10, time delay TD2, and positive And 12 is provided in a latch configuration which effectively stretches and shapes pulses A to the form shown in B. Each pulse B is of a duration approximately equal to the delay of TD 2 and is recurrent at period F. Pulses B are communicated via inverter 14 and line 16 to Or 18 which together with And 20 forms a latch having an output D. The first pulse on line 16 sets the latch bringing up output D and signaling the beginning of the monitored pulses A.

Pulses B are also supplied via line...