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J K Flip Flop

IP.com Disclosure Number: IPCOM000090435D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Maley, GA: AUTHOR

Abstract

Fabrication and implementation are simplified by constructing logical circuits from a basic building block or logic cell. A J-K flip-flop, drawing A, is constructed from individual cells each performing an And-Invert function. The J-K flip-flop or latch is shown in the set condition in which the set output line is in an up state. When the latch is reset, the set output line is in a down state. Both the J and K inputs are normally down. Raising the J input sets the flip-flop. Raising the K input resets the flip-flop. Raising both J and K inputs simultaneously, irrespective of minor timing differences, changes the state of the set output line. Similarly in B, an Eccles-Jordan type latch circuit is responsive to only the leading edges of incoming logical signals or the set and reset input lines.

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J K Flip Flop

Fabrication and implementation are simplified by constructing logical circuits from a basic building block or logic cell. A J-K flip-flop, drawing A, is constructed from individual cells each performing an And-Invert function. The J-K flip-flop or latch is shown in the set condition in which the set output line is in an up state. When the latch is reset, the set output line is in a down state. Both the J and K inputs are normally down. Raising the J input sets the flip-flop. Raising the K input resets the flip-flop. Raising both J and K inputs simultaneously, irrespective of minor timing differences, changes the state of the set output line. Similarly in B, an Eccles-Jordan type latch circuit is responsive to only the leading edges of incoming logical signals or the set and reset input lines. Thus without external capacitors or other circuit elements, the latch circuit functions as if its inputs are AC coupled. Both inputs are shown in their normally up state and the output is shown in the set condition in which the output line is in an up state. When the latch is reset, the output line is down. The latch is set or reset depending on which of its two inputs, set or reset, is brought to a down condition last. The output line does not change state if either or both of the input lines are raised to an up condition. If both input lines are simultaneously lowered to a down condition, the latch output changes state.

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