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Browse Prior Art Database

Skewed Control Storages to Increase Processor Throughput

IP.com Disclosure Number: IPCOM000090466D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Creamer, MK: AUTHOR [+2]

Abstract

This system provides skewing in the timing of a data processor to permit the status of several control storages to be interchanged without requiring extra operating cycles. Oscillator 3 provides clocking signals to clock controls 5 and 7, associated with micro-program control storages 9 and 11. Interposed between oscillator 3 and clock control 7 is time delay 13, which delays the supply of the clocking pulses to clock control 7 by some predetermined amount. Each control storage 9 and 11 has associated with it a status register such as status register 15 and status register 17. Control storage 9 governs the operation of arithmetic and logic section 19. Control storage 11 governs the operation of interface logic section 21. Input and output channels are connected to interface logic section 21.

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Skewed Control Storages to Increase Processor Throughput

This system provides skewing in the timing of a data processor to permit the status of several control storages to be interchanged without requiring extra operating cycles. Oscillator 3 provides clocking signals to clock controls 5 and 7, associated with micro-program control storages 9 and 11. Interposed between oscillator 3 and clock control 7 is time delay 13, which delays the supply of the clocking pulses to clock control 7 by some predetermined amount. Each control storage 9 and 11 has associated with it a status register such as status register 15 and status register 17. Control storage 9 governs the operation of arithmetic and logic section 19. Control storage 11 governs the operation of interface logic section 21. Input and output channels are connected to interface logic section
21. The operation control storages 9 and 11 is skewed by the amount of the time delay provided by time delay 13. Thus status registers 15 and 17 can control the address register of the opposite control storage in the same cycle.

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