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Logical Reduction of Scanning Data

IP.com Disclosure Number: IPCOM000090485D
Original Publication Date: 1969-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Meijer, E: AUTHOR [+2]

Abstract

In apparatus for recognition of stylized characters, data reduction is performed in order to match a high-resolution scanner to a low-resolution matrix register which is to store the scanned bit pattern for a character. High-resolution scanning is required to cope with print deviations such as fat and thin line widths or shadows. Reduced matrix dimension allows simpler recognition statements. Matching the two is feasible since no essential pattern information is lost in the reduction process.

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Logical Reduction of Scanning Data

In apparatus for recognition of stylized characters, data reduction is performed in order to match a high-resolution scanner to a low-resolution matrix register which is to store the scanned bit pattern for a character. High-resolution scanning is required to cope with print deviations such as fat and thin line widths or shadows. Reduced matrix dimension allows simpler recognition statements. Matching the two is feasible since no essential pattern information is lost in the reduction process.

Circuitry for a three-to-one data reduction comprises a number of parallel stage. .Each stage consists of threshold logic having six inputs and a single output, activated only when at least three out of the six inputs to the stage are active. Three inputs connect to consecutive bit lines from the scanner. The remaining three are biased by various collateral conditions, of which at most two can be active coincidently. Thus, from one to three scanned black bits are required, on a triple of bit input lines for transfer of one black output bit to the matrix. The actual threshold value at each output time depends on the present states of the collaterals as shown in this table.

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The table lists all possible cases between the four collateral conditions. Some states marked i are implied by the other conditions. Case 1 shows that, when no collateral is true, the threshold is 2 so the stage acts as majority circuit, 2/3 And, for the tr...