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Mosaic Image Sensor Cell

IP.com Disclosure Number: IPCOM000090488D
Original Publication Date: 1969-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Will, PM: AUTHOR

Abstract

This image sensor cell has a controllable storage feature. Such insures satisfactory response of the cell to light energy of low intensity integrated over a precise time interval. Each cell comprises photo diode 1, field effect transistors 2...4, and capacitor 6. Photodiodes 1 of the various cells are arranged in a mosaic which is exposed to light from the image being sensed. Closure of common integrate switch 5 gates FET 2 of each cell on, causing storage capacitor 6 of each cell to be charged by energy from photodiode 1 during a precisely timed interval while switch 5 is closed. Such interval is long enough to insure adequate charging of capacitor 6 even though the light intensity is low.

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Mosaic Image Sensor Cell

This image sensor cell has a controllable storage feature.

Such insures satisfactory response of the cell to light energy of low intensity integrated over a precise time interval. Each cell comprises photo diode 1, field effect transistors 2...4, and capacitor 6. Photodiodes 1 of the various cells are arranged in a mosaic which is exposed to light from the image being sensed. Closure of common integrate switch 5 gates FET 2 of each cell on, causing storage capacitor 6 of each cell to be charged by energy from photodiode 1 during a precisely timed interval while switch 5 is closed. Such interval is long enough to insure adequate charging of capacitor 6 even though the light intensity is low. Individual read select switch 7 of each cell is closed at a unique time, gating FET 4 on for applying to common read amplifier 8 the voltage stored in capacitor 6 of that cell. The cells are read in any arbitrary or random-access sequence. At the end of the reading operation, they are reset by closure of common reset switch 9 which gates FET 3 of each cell on to discharge associated capacitor 6. If for any reason it is desired to incorporate a prescribed lag in the response of the cell, this is accomplished by turning FET 3 partially on during the integrate time.

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