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Microprogramming Trap

IP.com Disclosure Number: IPCOM000090502D
Original Publication Date: 1969-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Spera, H: AUTHOR

Abstract

Servicing of microprogrammed computers is facilitated by a system which enables traps to be taken at any point in the micro-instruction routine. The condition which initiates the trap signal can be any logic level signal in the system. The micro-instruction routine can be varied to accommodate the analysis and storage of information corresponding to virtually any machine condition.

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Microprogramming Trap

Servicing of microprogrammed computers is facilitated by a system which enables traps to be taken at any point in the micro-instruction routine. The condition which initiates the trap signal can be any logic level signal in the system. The micro-instruction routine can be varied to accommodate the analysis and storage of information corresponding to virtually any machine condition.

The data flow chart shows the mode of operation. Assume that an intermittent error condition exists in the machine. A sequence of microinstructions related to this condition is loaded into a reserved area in storage. A test lead is then connected to a point in the computer which indicates the existence of the error condition. When a console switch is in the diagnostic position, the existence of a signal at the test lead connection causes the system to trap to the related sequence of micro-instructions. This sequence effects the logging of machine conditions, registers, and addresses in existence at the time the condition arises. Subsequent to the completion of this sequence, the main line program is re-entered and continued.

The devices which accomplish this function are activated by either Stop Diagnostic Switch 1 or Trap Diagnostic Switch 2. Where it is desired to stop the machine at the occurrence of a condition sensed by test lead 3, the output of latch 4 is combined with the switch 1 in And 5. The output from And 5 is a clock stop signal which disables machine clock 6. This enables a static analysis of the machine under conditions existent at the time the condition arises.

In the case of an infrequent fault, it can be inconvenient to stop the machine and hold up further operation until an analysis is performed. This is particularly true in the case of errors which are corr...