Browse Prior Art Database

Fabrication of PNP and NPN Transistors in a Single Wafer or Chip

IP.com Disclosure Number: IPCOM000090513D
Original Publication Date: 1969-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Chang, JJ: AUTHOR [+2]

Abstract

This process forms PNP and NPN transistors on the same substrate or wafer. The transistors are isolated from one another by isolation regions. They are also isolated from the substrate by intrinsic material. In one form, a P substrate 1 of silicon receives an N+ diffusion 2 to form a bed for the isolation of a subsequent PNP device. A thick N-epitaxial silicon layer 3 is deposited on substrate 1. N+ diffusions 4 are established in the layer to form the wall for the isolation of subsequent PNP transistors. P+ regions 5 are diffused into layer 3 for the isolation of subsequent NPN devices. N+ region 6 and P+ region 7 are formed in layer 3 as subcollectors.

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Fabrication of PNP and NPN Transistors in a Single Wafer or Chip

This process forms PNP and NPN transistors on the same substrate or wafer. The transistors are isolated from one another by isolation regions. They are also isolated from the substrate by intrinsic material. In one form, a P substrate 1 of silicon receives an N+ diffusion 2 to form a bed for the isolation of a subsequent PNP device. A thick N-epitaxial silicon layer 3 is deposited on substrate 1. N+ diffusions 4 are established in the layer to form the wall for the isolation of subsequent PNP transistors. P+ regions 5 are diffused into layer 3 for the isolation of subsequent NPN devices. N+ region 6 and P+ region 7 are formed in layer 3 as subcollectors.

A second N- epitaxial silicon layer 8 is deposited on the surface of layer 3. N+ diffusions 9 and 10 are formed in layer 8 as reach-throughs for NPN devices and for isolation of PNP devices. P+ regions 11 and 12 are formed in layer 8 as reach-throughs for PNP devices and for the isolation of NPN devices. A drive-in operation is performed to form N+ pockets for NPN and P+ pockets for PNP devices. This drive-in cycle also forms P+ enclosures for N+ pockets and N+ enclosures for P+ pockets. Base regions 13 and 14 are formed in NPN and PNP devices respectively. Gold is diffused into the N- layer 8 to form intrinsic regions which provide PIN isolation between the device and substrate. Gold diffusion can be omitted if intrinsic epitaxial layers instead of...