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Maintenance for Memory with Error Correction

IP.com Disclosure Number: IPCOM000090544D
Original Publication Date: 1969-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Beausoleil, WF: AUTHOR

Abstract

Words of memory can be stored in an error-correction code that permits correcting an error in any single bit position of a word that is read from the memory. Unless defects occur in two storage elements of the same word, such memory operates satisfactorily until its defective storage elements are located and corrected during a scheduled maintenance. The drawing shows such a memory in which storage elements can be assigned to different memory addresses so that two defective storage elements in the same word appear in different words where they produce correctable single errors.

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Maintenance for Memory with Error Correction

Words of memory can be stored in an error-correction code that permits correcting an error in any single bit position of a word that is read from the memory. Unless defects occur in two storage elements of the same word, such memory operates satisfactorily until its defective storage elements are located and corrected during a scheduled maintenance. The drawing shows such a memory in which storage elements can be assigned to different memory addresses so that two defective storage elements in the same word appear in different words where they produce correctable single errors.

Addressing circuit 2 is provided for the storage elements of each bit position
3. In normal operation, each position 3 receives the same four address A...D. The address decoder for each position 3 selects a correspondingly located storage element in each position 3 to form a memory word. The inputs to decoders 2 are connected to memory address bus 4 at a wiring panel where a wiring change converts an address bit to its complement value. The inputs to each decoder can be different so that each position 3 receives a different address in response to a particular address on bus 4. Numbers in the representation of a position 3 represent the location of the storage element that is accessed by the corresponding address on bus 4. For example, the address bits applied to bit position 0 are unchanged and the storage elements have the identification 0...15...