Browse Prior Art Database

Skewing Circuit for Byte Position Correction

IP.com Disclosure Number: IPCOM000090563D
Original Publication Date: 1969-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Andersen, LB: AUTHOR [+4]

Abstract

The skewing apparatus is for transmitting words between a buffer memory and a main memory. Lettered blocks represent bytes of memory words and illustrate a transfer from the buffer to the main memory. The apparatus includes gates 3 and 4 and a three-byte register 5 for skewing the bytes according to low-order bits of the main memory starting address 6. The apparatus permits loading the buffer while an operation takes place to fetch the starting address in main memory. If the main memory address does not begin on a word boundary, the bytes are appropriately skewed. In the example, the first two byte positions of the main memory word of the starting address are not available and are designated Y and Z. Solid lines show the interconnections through gates 3 and 4 and the active lines for the particular example.

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Skewing Circuit for Byte Position Correction

The skewing apparatus is for transmitting words between a buffer memory and a main memory. Lettered blocks represent bytes of memory words and illustrate a transfer from the buffer to the main memory. The apparatus includes gates 3 and 4 and a three-byte register 5 for skewing the bytes according to low- order bits of the main memory starting address 6. The apparatus permits loading the buffer while an operation takes place to fetch the starting address in main memory. If the main memory address does not begin on a word boundary, the bytes are appropriately skewed. In the example, the first two byte positions of the main memory word of the starting address are not available and are designated Y and Z. Solid lines show the interconnections through gates 3 and 4 and the active lines for the particular example. Dashed lines are not used in the example but are available for other skewing operations. In the first operation, bytes A...D are fetched from the buffer. Bytes A and B are transmitted through gate 3 to positions in main memory and bytes C and D are transferred through gate 4 to positions in register 5. In the next operation, bytes E...H are fetched from the buffer. Bytes C and D are transferred from register 5 through gate 3 to the main memory. Bytes E and F are transferred to the main memory along the path described for bytes A and B. Bytes G and H are transferred to register 5 along the path for bytes C and D and...