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Digital Pseudorandom Error and Burst Error Generator

IP.com Disclosure Number: IPCOM000090564D
Original Publication Date: 1969-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Frey, AH: AUTHOR [+2]

Abstract

The simulation of random and burst errors with selectable error density is accomplished by generating a random error injection signal with a fixed error density. This signal is passed through a multioutput delay line. One or more outputs of the delay line are selected simultaneously to generate the needed error injection signal. This creates a random error signal with selectable density. For burst error simulation, a timing pulse used as a gate is needed to bring a burst of errors with a selectable random density. By using a set of gates for random and another for burst error injection, both types of errors can be injected simultaneously as desired.

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Digital Pseudorandom Error and Burst Error Generator

The simulation of random and burst errors with selectable error density is accomplished by generating a random error injection signal with a fixed error density. This signal is passed through a multioutput delay line. One or more outputs of the delay line are selected simultaneously to generate the needed error injection signal. This creates a random error signal with selectable density. For burst error simulation, a timing pulse used as a gate is needed to bring a burst of errors with a selectable random density. By using a set of gates for random and another for burst error injection, both types of errors can be injected simultaneously as desired.

Drawing A shows the error generator logic and control inputs. These consist of pseudorandom error generator 1, burst error density gate 2 and control circuitry 3 and 4, random error density gates 5 and random error control circuitry 6, and output circuitry 7.

Drawing B shows pseudorandom error generator 1 which generates the random error injection signal with a fixed error density. Shift register 6 acts as a delay line with multiple outputs. Polynomial decoder 7 decodes the contents of register 6 and produces an output whenever the contents of such register 6 are of a desired value. The output of polynomial decoder 7 is used to inject 1's and 0's into register 6 and can be used as either a fixed signal with error density or data.

Drawing C shows the logic for a set...