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Buffer Store Replacement Control

IP.com Disclosure Number: IPCOM000090576D
Original Publication Date: 1969-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 37K

Publishing Venue

IBM

Related People

Boland, LJ: AUTHOR

Abstract

This data processing system has a memory hierarchy including a highspeed, low-capacity buffer store BS. Such is logically divided into a plurality of sets of blocks of words. There are four blocks in each set. Chronology array CA is used to control the filling and replacement of blocks within a set. The replacement is done according to the algorithm of replacing or overwriting the most remotely fetched-from block within a set.

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Buffer Store Replacement Control

This data processing system has a memory hierarchy including a highspeed, low-capacity buffer store BS. Such is logically divided into a plurality of sets of blocks of words. There are four blocks in each set. Chronology array CA is used to control the filling and replacement of blocks within a set. The replacement is done according to the algorithm of replacing or overwriting the most remotely fetched-from block within a set.

Data directory DD maps the contents of BS by storing the addresses of blocks written in BS. DD is composed of four independent random access devices that are addressed by the set address associated with a request. When a memory request is placed on buffer storage address bus BSAB, the set address of the request cycles DD to read out the four words associated with that particular set. These words contain the addresses of blocks in the corresponding locations of BS. The memory request is also placed into register BSAB R. Here the block address associated with a request is compared against the block addresses read out from DD. If the word is located in BS, then a match signal is fed to address translator AT whose output of two bits is combined with a partial buffer address, associated with the request, to form the final buffer address for accessing the desired location in BS.

Random access memory CA has a number of words corresponding to the number of sets in BS. Each word has six bits which reflect the order of fetching from the four blocks within a given set. Each time a word is fetched from BS, the match signal generated in association with the request actuates encoder ENC, in conjunction with the set address applied to it, and causes the appropriate word to be rewritten, without examining the current status, to reflect the order of fetching. The bits of the appropriate word of CA ar...