Browse Prior Art Database

Diode Load in NOR Block Circuit

IP.com Disclosure Number: IPCOM000090578D
Original Publication Date: 1969-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Terman, LM: AUTHOR

Abstract

A diode load is used in this Nor circuit. In A. a plurality of FET's, n-channel enhancement mode devices are assumed, is connected in parallel between an internal node 2 and ground 3. Logic inputs are connected to gates 4 of FET's 1. A charging pulse source 5 is connected through load diode 6 to node 2. With all logic inputs at a low value, FET's 1 nonconducting, node 2 is charged through diode 6. Node 2 is discharged when one or more of the logic inputs is high, i.e., when any or all FET's 1 are in a conducting state.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 90% of the total text.

Page 1 of 2

Diode Load in NOR Block Circuit

A diode load is used in this Nor circuit. In A. a plurality of FET's, n-channel enhancement mode devices are assumed, is connected in parallel between an internal node 2 and ground 3. Logic inputs are connected to gates 4 of FET's 1. A charging pulse source 5 is connected through load diode 6 to node 2. With all logic inputs at a low value, FET's 1 nonconducting, node 2 is charged through diode 6. Node 2 is discharged when one or more of the logic inputs is high, i.e., when any or all FET's 1 are in a conducting state.

For one pulsing sequence shown in B, the logic input is applied after termination of the charging pulse which has charged internal node 2 through diode 6.

Other pulsing sequences are possible. In C, logic inputs and charging pulses are applied simultaneously. Portions of them should at least overlap. Since the conductance of diode 6 is much greater than that of FET's 1, node 2 is charged up. When the charging pulse terminates, ode 2 is discharged except where all the logic inputs to FET's 1 are low. The connection of ground 3 to source 5 eliminates the possibility of current flowing between source 5 and ground which would cause loading of the charging pulse and power dissipation.

These arrangements are advantageous in that charging of node 2 is much faster than when an FET load device is used. The use of a diode results in smaller layout area and lower power dissipation in the integrated circuit environment. Also, lo...