Browse Prior Art Database

Hybrid Associative Memory

IP.com Disclosure Number: IPCOM000090579D
Original Publication Date: 1969-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

This associative memory uses both associative and nonassociative addressing. It includes several arrays of associative memory cells. Each array includes four words. Address decoder 3 decodes an address 4 to select one of the arrays for an associative operation. Search register 5 and word logic circuit 6 cooperate with the addressed array for conventional associative memory functions. Register 5 receives an interrogate word 7 and logic 6 energizes an output 8 that identifies the matched word or words of the addressed array.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 2

Hybrid Associative Memory

This associative memory uses both associative and nonassociative addressing. It includes several arrays of associative memory cells. Each array includes four words. Address decoder 3 decodes an address 4 to select one of the arrays for an associative operation. Search register 5 and word logic circuit 6 cooperate with the addressed array for conventional associative memory functions. Register 5 receives an interrogate word 7 and logic 6 energizes an output 8 that identifies the matched word or words of the addressed array.

The hybrid associative and nonassociative organization of this memory makes it suitable for monolithic construction where the number of signals that can be applied to a monolithic structure is limited. The number of wires required to carry word 7 is the same as for an equivalent fully associative memory. However, the number of wires required for address 4 and for output 8 of logic 6 is significantly smaller than the number of word logic output wires for a fully associative memory.

There are important applications for associative memories in which part of the addressing can be nonassociative. This hybrid associative memory is arranged to translate an address 9 for a large capacity memory into a corresponding address for a smaller buffer memory 12. Sections of memory 12 are conventionally addressed according to the block and lower bits of the address. The hybrid associative memory locates the section of the memory in whi...