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ALU Parity Predictor and Checker

IP.com Disclosure Number: IPCOM000090588D
Original Publication Date: 1969-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Lewis, PJ: AUTHOR [+2]

Abstract

This is a parity predictor and carry checker for the Arithmetic Logic Unit ALU of a data processor. The carry generation within ALU is checked by performing a duplicate carry generation and comparing the results of the two carry circuits. At the same time the carry generators are being checked, the predicted parity of the generated sum of the factors entered into the ALU is formed from the known parity of the input factors together with the generated parity of the carries from the duplicated carries.

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ALU Parity Predictor and Checker

This is a parity predictor and carry checker for the Arithmetic Logic Unit ALU of a data processor. The carry generation within ALU is checked by performing a duplicate carry generation and comparing the results of the two carry circuits. At the same time the carry generators are being checked, the predicted parity of the generated sum of the factors entered into the ALU is formed from the known parity of the input factors together with the generated parity of the carries from the duplicated carries.

The generated carry term for the lowest denominational order is provided by And's 10A, 11A, and 12A. Each has as its inputs a different combination of two of the three bits comprised of the low-order bits of the two factors to be added and the carry input to the lowest order. The outputs And's 10A, 11A, and 12A are combined in Or-Inverter 0I 13A. This which has a low-level output when any input to it is at a high level, i.e., the output of OI 13A is low whenever a carry is to be generated in the first stage. For the second denomination, And's 10B, 11B, and 12B, and OI 13B similarly drop the output of OI 13B whenever a carry is to be generated in the second denominational orders. There is a difference in the carry input circuit for the second denomination. The output of OI 13A is used as the carry input and since it is at a complemental signal level, it is passed through inverter 19B whose output is the carry input to And's 11B and 12B. The carry generating circuit of the second denomination is duplicated for the intermediate denominations and ends at And's 10N, 11N, 12N, and OI 13N of the highest order.

To test for the occurrence of an erroneous carr...