Browse Prior Art Database

Clock

IP.com Disclosure Number: IPCOM000090661D
Original Publication Date: 1969-Jun-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 68K

Publishing Venue

IBM

Related People

Carnevale, RJ: AUTHOR [+2]

Abstract

This clock, drawing A, has a plurality of DC latches. These respond alternatively to rising or falling edges of an input oscillator signal under control of signals which determine the length of each full cycle. These individual cycles are 180, 225 or 270 ns long as commanded by the control signals. In addition, an error recycle is included which forces the clock to keep taking 0 time cycles until the error signal is eliminated. The clock includes a plurality of And-Or latches identified as 0 time, 0 time delay, 1 time, 1 time delay, 2 time and 2 time delay. Each latch produces at its output complementary signals identified by the same name.

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Clock

This clock, drawing A, has a plurality of DC latches. These respond alternatively to rising or falling edges of an input oscillator signal under control of signals which determine the length of each full cycle. These individual cycles are 180, 225 or 270 ns long as commanded by the control signals. In addition, an error recycle is included which forces the clock to keep taking 0 time cycles until the error signal is eliminated. The clock includes a plurality of And-Or latches identified as 0 time, 0 time delay, 1 time, 1 time delay, 2 time and 2 time delay. Each latch produces at its output complementary signals identified by the same name.

Oscillator 1 A is coupled to Exclusive-Or 2. The other input to Exclusive-Or 2 is the output of bistable multivibrator 3. The output of Exclusive-Or 2 is connected to noninverting driver 4 via delay circuit 5. The amount of delay in signals coupled from circuit 2 to circuit 4 can be set to any desired one of the plurality of values available in delay 5. Complementary output signals from driver 4 are applied to the +Osc and -OSC lines. The -OSC line is connected to various inputs of latches 0 time, 1 time, and 2 time. The +Osc line is applied to various inputs of the latches 0 time delay, 1 time delay, and 2 time delay. As in B, 180, 225 or 270 cycle times can be selected, depending upon control inputs to the clock.

When the clock is initially turned on for operation, reset line 10 applies signals via Or 11 to latches 0 time, 0 time delay, 1 time, 1 time delay, and 2 time to turn these latches off and, at the same time, turns 2 time delay latch on. The plus clock start reset signal is applied to multivibrator 3 to force it to its reset state in which its output applies a positive signal to Exclusive-Or 2. This causes the output of Exclusive-Or 2 to be in phase with the oscillator 1 signals applied to its input. This, in turn, causes the signals on the -Osc line to be in phase with the output signals from oscillator 1 and Exclusive-Or 2 and the signals on the +Osc line to be 180 degrees out of phase.

The output signals from oscillator 1 have no effect on the latches of the clock until such time as the -clock start input signal is applied to terminal 12 and to selected inputs of And's 13, 14, and 15 of the 0 time latch. Since the reset turns on the -2 time delay latch, a negative signal is applied to And 15. As soon as the -Osc line goes negative, the And function for circuit 15 is satisfied, thus turning the 0 time latch on. A latch-back connection from the negative output of the 0 time latch into And 16 together with the reset signal, which is maintained negative during operation of the clock, maintains the 0 time latch in its latched-up state. At 45 time in the cycle, drawing B, the -Osc line goes positive and the +OSC line goes negative, satisfying the input conditions for And 17 or the 0 time delay latch turning the latter on. A feedback to its associated And 18 holds the latch on. At 9...