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Table Look Up Pipeline

IP.com Disclosure Number: IPCOM000090664D
Original Publication Date: 1969-Jun-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Bliss, BE: AUTHOR [+2]

Abstract

An n-stage data pipeline processes a stream of data from indexer A0 with operators from indexers A1...An. The pipeline includes a series of monolithic memory arrays M1...Mn, each having its own storage address register SAR. Indexers A0...An are also monolithic memory arrays. Indexers A0...An are loaded with count and data fields. Starting addresses a0...an are fed to the indexers at the start of the pipelining, to read out data A0...An and count fields that are fed back to provide addresses for the next machine cycle. The count fields cause data to be read from the indexers on either a sequential or a nonsequential basis according to the manner of loading the count fields. Data A0 and A1 from indexers A0 and A1 are supplied on each machine cycle to the SAR of M1, i.e., the first stage of the pipeline.

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Table Look Up Pipeline

An n-stage data pipeline processes a stream of data from indexer A0 with operators from indexers A1...An. The pipeline includes a series of monolithic memory arrays M1...Mn, each having its own storage address register SAR. Indexers A0...An are also monolithic memory arrays. Indexers A0...An are loaded with count and data fields. Starting addresses a0...an are fed to the indexers at the start of the pipelining, to read out data A0...An and count fields that are fed back to provide addresses for the next machine cycle. The count fields cause data to be read from the indexers on either a sequential or a nonsequential basis according to the manner of loading the count fields. Data A0 and A1 from indexers A0 and A1 are supplied on each machine cycle to the SAR of M1, i.e., the first stage of the pipeline. The contents of the memory address defined by A0 and A1 are the result of the operation A0 and A1. The operation can be arithmetical, logical, etc. The output or result from M1 is fed as an address input to M2 along with data A2. The output of indexer A2, and of the remaining indexers, is delayed appropriate o provide data for the higher stages ~o the pipeline. M...Mn can contain tables for multiple operations using addresses I1...In. These addresses are supplied from an external control unit or as a function of the indexer data outputs.

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