Browse Prior Art Database

Data Stream Analysis Device

IP.com Disclosure Number: IPCOM000090691D
Original Publication Date: 1969-Jun-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Sakalay, FE: AUTHOR

Abstract

The monitoring system is for detecting known or unknown loops in a program sequence in a computer system. Shift register 10 has a plurality of parallel sections 10a...10n. Each section such as 10n comprises a plurality of parallel stages 1...n. Thus the input from a computer, such as instruction operation codes, can have all bits provided in parallel to the input of register 10. A shift timing input is also provided to shift the data input between times when the data input is received.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 69% of the total text.

Page 1 of 2

Data Stream Analysis Device

The monitoring system is for detecting known or unknown loops in a program sequence in a computer system. Shift register 10 has a plurality of parallel sections 10a...10n. Each section such as 10n comprises a plurality of parallel stages 1...n. Thus the input from a computer, such as instruction operation codes, can have all bits provided in parallel to the input of register 10. A shift timing input is also provided to shift the data input between times when the data input is received.

A plurality of comparators 11b...11n is respectively connected between the last shift stage 10a and each of the other shift stages 10b... 10n respectively. Each comparator compares in parallel the corresponding bit positions in its two inputs. Counters 12b...12n are respectively connected to the outputs of comparators 11b...11n. The output of a given comparator indicates the existence of a loop.

In operation, the input stream progresses through register 10. When the data reaches the last stage 10a, an equal compare is made between this stage and all previous stages simultaneously. If an equal condition occurs with any comparator, the counter associated with that comparator is stepped. If an equal condition does not occur for any comparator, its counter is reset. This comparator operation thus occurs each time the data in register 10 is shifted by one stage.

For example, consider a twelve instruction loop is being shifted through the sequencer. When the f...