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Indirect Addressing Prefix Instruction

IP.com Disclosure Number: IPCOM000090692D
Original Publication Date: 1969-Jun-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 25K

Publishing Venue

IBM

Related People

Clark, WA: AUTHOR [+2]

Abstract

Each instruction PX or PI is a prefix to an object instruction immediately following it. No interruption can occur between the fetch of the prefix instruction and the fetch of its object instruction. Hence the prefix instruction and its object instruction comprise a single executable entity. On interrupt, the object instruction length code is stored.

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Indirect Addressing Prefix Instruction

Each instruction PX or PI is a prefix to an object instruction immediately following it. No interruption can occur between the fetch of the prefix instruction and the fetch of its object instruction. Hence the prefix instruction and its object instruction comprise a single executable entity. On interrupt, the object instruction length code is stored.

For PX, the contents of the general purpose registers specified by R1 and R2, respectively, are used in the generation of the first and second operand address of the object instruction. If register 0 is specified for either R1 or R2, the generation of the corresponding operand address takes place normally. The register named by a field in the prefix instruction is disregarded if the object instruction generates no effective address for the corresponding operand.

The PX instruction can be used to apply an index to either or both of the operands of a Storage to Storage SS Instruction, and to the single operands of a Storage and Intermediate SI or Register and Storage RS instruction. It can also be used to specify double indexing of the second operand of a Register and Indexed Storage RX instruction. It is meaningless when applied to a Register to Register RR instruction.

With the PI instruction, its second byte consists of two 4-bit immediate operands I1 and I2. Each specifies how the corresponding operand address in the object instruction is to be interpreted in the following manner. I = 0 implies that the corresponding operand is to be

interpreted normally.

I not = 0 implies that if the corresponding operand specifies

a memory address, the content of the field beginning

at this memory address specifies the address of the

corresponding operand according to the bits of I.

If the corresponding operand specifies a register, I

is ignored.

The four bits, left to right, of either I1 or I2 are interpreted in this manner.

Bit If 0 If 1 0 The field in memory contains the The field in memory effective address of the operand. contains

the address of the operand

in the form D(B), where

the register B is specified

by the 4 high-order bits

of the field and D by the

remaining bits. 1 The field in memory is four bytes The field...