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Redundancy Technique for Crystal Oscillators

IP.com Disclosure Number: IPCOM000090713D
Original Publication Date: 1969-Jun-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Duke, KA: AUTHOR [+2]

Abstract

In any computer or complex electronic system where a system clock is the basic source of all timing pulses, it is essential to maintain the highest possible reliability in the central clock, usually an oscillator. In addition, in redundant oscillator systems, at least one standby oscillator, switching transients cause serious disruptions in the system. A transient of excessive duration can occur when one of the spare redundant oscillators needs to be activated because of failure in the active oscillator. No output is apparent until the spare oscillator of the reaches a minimum amplitude. In this system, OSC1 provides the output initially. OSC2, although oscillating, is inhibited by Gate 2 from transmitting a signal to the output. OSC3 is off and remains so until either of the other two oscillators fails.

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Redundancy Technique for Crystal Oscillators

In any computer or complex electronic system where a system clock is the basic source of all timing pulses, it is essential to maintain the highest possible reliability in the central clock, usually an oscillator. In addition, in redundant oscillator systems, at least one standby oscillator, switching transients cause serious disruptions in the system. A transient of excessive duration can occur when one of the spare redundant oscillators needs to be activated because of failure in the active oscillator. No output is apparent until the spare oscillator of the reaches a minimum amplitude. In this system, OSC1 provides the output initially. OSC2, although oscillating, is inhibited by Gate 2 from transmitting a signal to the output. OSC3 is off and remains so until either of the other two oscillators fails. The SYNC's provide synchronization and phase-lock between all three oscillators.

When power is initially turned on, the output signal is generated by OSC1. Suppose OSC1 fails. Such a failure is detected by Detector 1 which recognizes that the amplitude or frequency of the oscillator's signal is changing. When OSC1 and OSC2 are functioning Properly, the outputs of Detectors 1 and 2 are 1's. Assume that the Detectors recognize changes in amplitude. Once the signal decreases to below a minimum level, a binary 0 appears at the upper input of And 4. This inhibits Gate 10 and, in turn, forces the output of Inverter 5 to be a...