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Fast Decode Circuit

IP.com Disclosure Number: IPCOM000090733D
Original Publication Date: 1969-Jun-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Berding, AR: AUTHOR

Abstract

This circuit decodes a plurality of inputs in one logic stage. For any computer storage, it is necessary to retrieve or access the stored information as rapidly as possible. However, there are usually several steps that have to be performed after receiving an address and before an access line can be energized. First, the address lines are powered up so that they can drive many circuits. Second, both true and complement polarities of each address line are generated. Third, these lines are decoded into a unique address. Further, this decoded output is powered up to drive the access line which is usually loaded by many storage elements.

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Fast Decode Circuit

This circuit decodes a plurality of inputs in one logic stage. For any computer storage, it is necessary to retrieve or access the stored information as rapidly as possible. However, there are usually several steps that have to be performed after receiving an address and before an access line can be energized. First, the address lines are powered up so that they can drive many circuits. Second, both true and complement polarities of each address line are generated. Third, these lines are decoded into a unique address. Further, this decoded output is powered up to drive the access line which is usually loaded by many storage elements.

This fast decode circuit accomplishes all four steps in a single logic step. For example, a one-out-of-four arrangement is shown. For the A input, input transistor T1 provides powering, the current switch comprising T2 and T3 generates both true and complement polarities, diodes T4...T7 decode the address, and one output emitter-follower T15 T16, T17 or T18 powers the decode output.

The corresponding transistors shown for input B perform the corresponding functions. In performing the decode function, only one output G, H, J or K can be at an up level at any time.

For example, if the inputs to T1 and T8 are up then T2 and T9 conduct and T3 and T10 are off. Since T2 is on, it holds down the base of both T18 and T17 through diodes T4 and T5 respectively. Since T9 is on, it holds down the base of T16 through diode 12....