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Insulated Gate Field Effect Pinch Off Device

IP.com Disclosure Number: IPCOM000090754D
Original Publication Date: 1969-Jun-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Gaensslen, FH: AUTHOR

Abstract

In this structure, enhancement and depletion mode field effect devices are placed on the same substrate by a technique which requires only a single additional diffusion. In addition to the usual source-drain diffusion, shallow diffusion is required to interconnect the source and drain regions where a pinch-off device is desired. The resulting structure consists of semiconductor substrate 1 into which diffusions 2 of the same conductivity type are made to form the source and drain regions of field effect transistors. Diffusions 2 are formed by the usual photolithographic and etching techniques which open windows in SiO(2) layer 3 through which appropriate dopants are introduced by diffusion. The left-hand device is an enhancement mode type of field effect transistor.

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Insulated Gate Field Effect Pinch Off Device

In this structure, enhancement and depletion mode field effect devices are placed on the same substrate by a technique which requires only a single additional diffusion. In addition to the usual source-drain diffusion, shallow diffusion is required to interconnect the source and drain regions where a pinch- off device is desired. The resulting structure consists of semiconductor substrate 1 into which diffusions 2 of the same conductivity type are made to form the source and drain regions of field effect transistors. Diffusions 2 are formed by the usual photolithographic and etching techniques which open windows in SiO(2) layer 3 through which appropriate dopants are introduced by diffusion. The left- hand device is an enhancement mode type of field effect transistor. The right- hand device is a depletion mode type of field effect transistor. Such type requires the presence of diffused channel 4 interconnecting its source and drain. This is accomplished by forming an opening by photolithographic techniques in layer 3 between source and drain diffusions 2, and diffusing an appropriate dopant through the opening to form the required 4. In a final step, SiO(2) is removed between the source and drain diffusion of both devices and a thin layer of SiO(2), gate oxide, is re-formed in the openings. Gate metallizations and contacts, not shown, are applied by conventional techniques. In this arrangement, the source and drain reg...