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Table Look Up Carry Select Adder

IP.com Disclosure Number: IPCOM000090783D
Original Publication Date: 1969-Jul-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Bliss, BE: AUTHOR [+2]

Abstract

In table look-up addition, the required amount of storage increases greatly as the operand size increases. The drawing shows a way to minimize this problem. Operands A and B are placed in registers 10 and 11. Each register is divided into stages 1...4, each containing the same number of orders or bits. The outputs of corresponding stages, e.g., stage 3, are fed as arguments to storage address register SAR of storage device 12 associated with the stage. Each stage has a similar device although only one is shown. Device 12 is loaded with data arranged in fields to provide the results of addition and subtraction both without and with a carry in Ci from a low-order stage. Propagate P and generate G fields provide bits for use by carry look-ahead circuits 13, common to all stages.

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Table Look Up Carry Select Adder

In table look-up addition, the required amount of storage increases greatly as the operand size increases. The drawing shows a way to minimize this problem. Operands A and B are placed in registers 10 and 11. Each register is divided into stages 1...4, each containing the same number of orders or bits. The outputs of corresponding stages, e.g., stage 3, are fed as arguments to storage address register SAR of storage device 12 associated with the stage. Each stage has a similar device although only one is shown. Device 12 is loaded with data arranged in fields to provide the results of addition and subtraction both without and with a carry in Ci from a low-order stage. Propagate P and generate G fields provide bits for use by carry look-ahead circuits 13, common to all stages. The results of an addition or subtraction are read into storage data register SDR. From SDR, the P and G outputs are fed to 13 for out-gating the correct sum S (Ci) or S (Ci) from the fourth or high-order stage in accordance with the particular carry conditions. The correct sum S (Ci) or S (Ci) from stage 3 is controlled by the P and G bits from stage 2. When the operands are placed in SAR, device 12 is cycled. The results are read into SDR in the middle of the cycle and are held there until the end of the cycle. Circuits 13 operate, while the results are in SDR, to gate the sum before the end of the cycle.

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