Browse Prior Art Database

Writing in Memory without First Reading

IP.com Disclosure Number: IPCOM000090784D
Original Publication Date: 1969-Jul-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Hartlipp, WE: AUTHOR [+2]

Abstract

The effective speed of memory operation can be greatly increased by eliminating the need to precede each write operation with a read operation. In existing memories, a read operation, resetting the addressed cores to 0's, always precedes a write operation. If only writing is desired, the time needed for reading is wasted. In this method, addressed cores are written into without a preceding read operation. Each core requires at least two half-select drives, of which only one is shown. When writing 1's the current is supplied in the write direction, while 0's are written by a reverse current read direction. When reading, the current is supplied in the direction of the arrow marked read to reset all cores to 0 in the normal manner.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Writing in Memory without First Reading

The effective speed of memory operation can be greatly increased by eliminating the need to precede each write operation with a read operation. In existing memories, a read operation, resetting the addressed cores to 0's, always precedes a write operation. If only writing is desired, the time needed for reading is wasted. In this method, addressed cores are written into without a preceding read operation. Each core requires at least two half-select drives, of which only one is shown. When writing 1's the current is supplied in the write direction, while 0's are written by a reverse current read direction. When reading, the current is supplied in the direction of the arrow marked read to reset all cores to 0 in the normal manner. The current direction is controlled by supplying signals to a solid-state double-pole double-throw switch. If a read cycle is desired, the X lines are activated to cause current to flow through the line of cores in the normal read direction. If a write operation requiring the writing of a 0 bit is desired, X signals are also supplied. If it is desired to write a 1 bit, the Y signals are supplied to the transistors causing the current to flow through the line of cores in the opposite write direction. The cores are forced to take whatever state is desired regardless of their previous setting.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]