Browse Prior Art Database

Clock Gated Flip Flop

IP.com Disclosure Number: IPCOM000090802D
Original Publication Date: 1969-Jul-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Elliott, JE: AUTHOR

Abstract

This flip-flop gating configuration lends itself to monolithic construction. Self-gated flip-flop 10, consisting of flip-flop 12 and And's 14 and 16, is triggered by an output of Or 18. The latter can be built to respond to any number of And's 20 and is sampled by a clock signal over line 22. In operation, flip-flop 10 changes state each time Or 18 has an output. So long as any of And's 20 has an output, the output from Or 18 does not change, irrespective of clock pulses over line 22. However, if none of And's 20 are satisfied, the next clock pulse 22 causes flip-flop 10 to change state. Various logical configurations can be formed by interconnecting module circuits of this type Any number of And's can be applied to Or 18.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Clock Gated Flip Flop

This flip-flop gating configuration lends itself to monolithic construction. Self-gated flip-flop 10, consisting of flip-flop 12 and And's 14 and 16, is triggered by an output of Or 18.

The latter can be built to respond to any number of And's 20 and is sampled by a clock signal over line 22. In operation, flip-flop 10 changes state each time Or 18 has an output. So long as any of And's 20 has an output, the output from Or 18 does not change, irrespective of clock pulses over line 22. However, if none of And's 20 are satisfied, the next clock pulse 22 causes flip-flop 10 to change state. Various logical configurations can be formed by interconnecting module circuits of this type Any number of And's can be applied to Or 18. An advantage of the configuration is that it operates with DC levels and does not require an AC set signal.

1

Page 2 of 2

2

[This page contains 1 picture or other non-text object]