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High Speed Serial Circuits

IP.com Disclosure Number: IPCOM000090810D
Original Publication Date: 1969-Jul-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Calvert, JD: AUTHOR [+2]

Abstract

Several circuits are shown utilizing the principle of a saturated transistor gate. The characteristics of the gate are a normal turnon time for conditioning of the date or a network of gates combined with extremely low transmission delays through the gate after the conditioning is completed. The signal propagation delay through a saturated transistor is too small to measure. Connecting several transistors in series amounts to essentially only the additional series resistance of 6 to 10 ohms per transistor. These characteristics are utilized in the very high-speed circuits shown, such as parity, error-correcting code, decoder, compare and adder carry circuits.

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High Speed Serial Circuits

Several circuits are shown utilizing the principle of a saturated transistor gate. The characteristics of the gate are a normal turnon time for conditioning of the date or a network of gates combined with extremely low transmission delays through the gate after the conditioning is completed. The signal propagation delay through a saturated transistor is too small to measure. Connecting several transistors in series amounts to essentially only the additional series resistance of 6 to 10 ohms per transistor. These characteristics are utilized in the very high- speed circuits shown, such as parity, error-correcting code, decoder, compare and adder carry circuits.

The logical requirements are as follows. The circuit logic has to be such that the reverse action of the collector and emitter when voltages are reversed either cannot occur due to the base signal level or does not cause a back circuit logic problem if it does occur. The circuit logic is such that the elements in the series circuit are conditioned in parallel so that only a single turnon delay occurs. Parity generator A utilizes these high-speed characteristics. The input drive to the series chain can be a permanent bias voltage in cases where no look-ahead can be realized by prior conditioning of the series circuit elements. Much higher circuit speed can be realized if the input collector drive is a sample signal which occurs after the circuit is conditioned. Once the latches L1...Ln settle down to their steady state conditions and the appropriate transistors are energized, a sample signal on the Drive In lin...