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High Performance Minimal Cycle Control Store Configuration

IP.com Disclosure Number: IPCOM000090846D
Original Publication Date: 1969-Jul-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Dailey, JR: AUTHOR [+2]

Abstract

Minimum accessing of control storage 5 is achieved in a microprogrammed processor. Storage 5 is oriented to a flexible memory structure having control word locations arranged in rows with as many locations n in a row as there are control word storage positions, e.g., five, in output register 6. Instead of accessing one row of control words at a time, two rows are accessed simultaneously for five control words, beginning with the first to be executed to minimize the number of accesses.

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High Performance Minimal Cycle Control Store Configuration

Minimum accessing of control storage 5 is achieved in a microprogrammed processor. Storage 5 is oriented to a flexible memory structure having control word locations arranged in rows with as many locations n in a row as there are control word storage positions, e.g., five, in output register 6. Instead of accessing one row of control words at a time, two rows are accessed simultaneously for five control words, beginning with the first to be executed to minimize the number of accesses.

A macro-word, entered into the register 1, contains the address of its first control word, the length L of operation, i.e., the number of control words required to complete the operation, and the branch address to the next macro-word. This information is decoded in control store address decode 2 to address the first control word which, for example, is stored in location Yi Xk. This data is also sent to ring modulo-n counter 3 which begins at a stage corresponding to the addressed Yi location. Since a double row of storage is accessed during one cycle, the first control word and the next four words are assembled in 4 and entered into 6. Word selector 7, under the control of 3, gates the control words one through five in sequence to a control decode which feeds all of the control points of the processor. After decode and execution of the five words, a comparator in 3 causes the reset of 6, stops the counter, and depending on w...