Browse Prior Art Database

Short Circuit Test Device

IP.com Disclosure Number: IPCOM000090870D
Original Publication Date: 1969-Aug-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Ravoux, D: AUTHOR

Abstract

The device detects short circuits in switching networks having semiconductor controlled rectifiers as crosspoint switches.

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Short Circuit Test Device

The device detects short circuits in switching networks having semiconductor controlled rectifiers as crosspoint switches.

The DC path in a telephone switching network extends between subscriber transformer ST and terminal junctor TJ5. This DC path comprises controlled rectifier gates CA...CF for matrix levels A...F and feeders FC and FF. This path is established in two steps. In the first, FC is switched on and CA, CB, and CC are fed with a control pulse. DC current flows now from the 24V source to ground through CA, CB, CC, and FC. In the step, FF is switched on and CD, CE, and CF are fed with a control pulse. DC current flows also through CD, CE, CF, feeder FF and ground. If subscriber S is only to be connected to median junctor M5, only the first step is used.

This device detects short circuits occurring between the C level matrix outputs and ground GC and between the F level matrix outputs and ground GF. It also detects if a feeder is erroneously on or short circuited. The test device is composed of a test network which is a three-input switching matrix TN having controlled rectifiers as crosspoint switches, three limit-detectors LD1, LD2, LD3 through which the three test network input lines are connected to a +24 V source, and majority circuit MC which controls an alarm device AL in case two or three detectors detect a current.

Each output line of TN is connectable through controlled rectifiers to several output lines from the C level matrix. For example, output line LT1 is connectable respectively to lines LCA, LCB, and LCC through rectifiers CRA, CRB, and CRC. Output line LT2 is connectable to three other lines from C level matrices through three other controlled rectifiers, etc. In addition, the gates of al...