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Decimal Adder

IP.com Disclosure Number: IPCOM000090876D
Original Publication Date: 1969-Aug-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Schmookler, MS: AUTHOR [+2]

Abstract

This decimal adder makes use of don't-care conditions and logic function dotting in generating the corrected sum.

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Decimal Adder

This decimal adder makes use of don't-care conditions and logic function dotting in generating the corrected sum.

Two digits of the decimal adder are shown at 1. The corrected sums S1c...S8c are provided in three circuit levels from the sets of single phase inputs A1 and B1...A8 and B8. The P and G signals denote the propagate and generate functions.

The third level logic circuits of the adder provide the corrected binary sums which together equal the decimal sum. A third level circuit for a decimal digit is at
2. Each decimal digit requires seven current switching gates which are capable of providing both Or and Nor outputs.

The logic conditions that are satisfied in the third logic level to provide the corrected binary sums, where CDec is the decimal carry, are: S1c = S1 S2c = CDecS2 + CDecS2 = CDecS2 + CDec + S2 S4c = CDecS4S2 + CDecS4S2 + CDecS4 = (CDec + S2) S4 + CDec + S4 + S2 S8c = CdecS8S4S2 + CDecS8S4 + CDecS8S2 + CDecS8. The first two terms of this expression are invalid terms and therefore: S8c = CDecS8S2 + CDecS8 = G8 + C1 + CDec + C4 + P8. The expressions indicate that it is not necessary to develop the binary sum S8, as (C4 + P8) can be used in its place.

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