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Clock Speed Control Circuit

IP.com Disclosure Number: IPCOM000090890D
Original Publication Date: 1969-Aug-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Martin, VC: AUTHOR

Abstract

Reasonable synchronization is maintained between displacement and the occurrence of a repetitive event where some variation of a number of events can be tolerated for a given displacement, but such variations cannot be permitted to accumulate over a sequence of such displacements. The device makes it possible to use tachometers which have slightly irregular spacings between displacement indicating output pulses by continuously monitoring these pulses and increasing or decreasing the repetition rate of the event controlling clock.

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Clock Speed Control Circuit

Reasonable synchronization is maintained between displacement and the occurrence of a repetitive event where some variation of a number of events can be tolerated for a given displacement, but such variations cannot be permitted to accumulate over a sequence of such displacements. The device makes it possible to use tachometers which have slightly irregular spacings between displacement indicating output pulses by continuously monitoring these pulses and increasing or decreasing the repetition rate of the event controlling clock.

The circuitry is used in conjunction with a system in which sixteen events are intended to occur between each pair of tachometer displacement indicating pulses, but in which the occurrence of such tachometer pulses before four events occur or after twelve events occur can be tolerated. That is, the system has a tolerance of plus or minus four events between each pair of tachometer pulses, but the occurrence of events within tolerance cannot be permitted to accumulate. Tachometer output pulses are introduced to the circuitry at each terminal T. All latches and counters are initially reset or cleared.

A start signal at terminal 20 partly conditions And 21 which becomes completely conditioned at the occurrence of the next T. At that time, latch 22 is set so that And 23 begins gating pulses from crystal controlled oscillator 25 into clock counter 26. The latter reaches a high count which is indicated on line 27, thus completing conditioning of And 28 and Or 29. Single-shot 30 then produces an output pulse on line 32 which resets counter 26 through Or 33 and which causes the event to occur. This same pulse on line 32 is introduced to terminal 34 and causes one count to be stored in counter 35. Counts continue to be sensed in 26, produced at 32, and counted by 35 until the fifth count is present in
35. At this time And 36 is conditioned and causes emitter storage latch 38 to be reset. Counter 35 continues to be incremented until the sixteenth count is stored in it and causes single-shot 39 to sample And's 40 and 41. If no T pulses occur before sixteen is counted, latch 44 continues to be reset and line 45 continues to be raised so that 26 continues to count to the maximum count, as indicated by pulses on 27. The maintaining of 45 up indicates too many event controlling pulses 32 occur between T pulses and has the effect of increasing the time between pulses 32.

If pulses 32 do not occur fast enough, a T pulse sets 38 before 35 contains a count of sixteen. As a resu...