Browse Prior Art Database

Partial Two Way Mapping Technique

IP.com Disclosure Number: IPCOM000090910D
Original Publication Date: 1969-Aug-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Ofek, H: AUTHOR [+2]

Abstract

The system is for mapping A addresses on input line 2 into B addresses on output line 3. An A address can be supplied by a CPU to identify an I/O unit that is connected to the CPU through a crosspoint switch. The B address identifies the path through the crosspoint switch to reach the I/O unit. As the crosspoint switch is changed, the mapping is correspondingly changed. In the example in the drawing, A address 101 is transmitted through an Or to storage address register 4. The latter supplies the address to decoding circuit 5 of memory 6 which supplies the B address 011 to memory data register 8.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Partial Two Way Mapping Technique

The system is for mapping A addresses on input line 2 into B addresses on output line 3. An A address can be supplied by a CPU to identify an I/O unit that is connected to the CPU through a crosspoint switch. The B address identifies the path through the crosspoint switch to reach the I/O unit. As the crosspoint switch is changed, the mapping is correspondingly changed. In the example in the drawing, A address 101 is transmitted through an Or to storage address register 4. The latter supplies the address to decoding circuit 5 of memory 6 which supplies the B address 011 to memory data register 8.

The system simplifies the mapping for a crosspoint switch that has a small number of inputs and a large number of outputs. In the example, there are eight B addresses but only four of them can be connected through the crosspoint switch at any one time. The rightmost bit position of memory 6 contains a 1 to signify an active connection or a 0 to signify that a remapping may be necessary to establish a connection. Memory 6 has a D field containing data that is useful in remapping. For example, the D field can indicate that a particular connection is not available or it can contain priority assignments. Decode logic circuit 9 decodes the active bit and the D field and supplies addresses to the Or as appropriate to search through the memory for a suitable remapping.

The logic controlling the remapping is simplified by arranging the relations...