Browse Prior Art Database

Uniform Temperature Control of Semiconductor Wafer Under Test

IP.com Disclosure Number: IPCOM000090965D
Original Publication Date: 1969-Sep-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Chu, RC: AUTHOR

Abstract

In testing multichip wafers 10, it is desirable to obtain a uniform temperature over the entire wafer. Chips 12, situated further away from the center or near the periphery, receive less cooling than chips 12 that are near the center. This variation of the temperature from center to periphery is corrected by placing concentric grooves 14 on temperature platform 16 which are spaced proportionally to the temperature differential. This technique mechanically corrects the effective heat conduction area of a chip 12 considering its location on wafer 10. Those chips 12 near the center of wafer 10 have more grooves 14 underneath and thus less effective thermal conduction. Peripheral chips 12 see fewer or no grooves 14 at all.

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Uniform Temperature Control of Semiconductor Wafer Under Test

In testing multichip wafers 10, it is desirable to obtain a uniform temperature over the entire wafer. Chips 12, situated further away from the center or near the periphery, receive less cooling than chips 12 that are near the center. This variation of the temperature from center to periphery is corrected by placing concentric grooves 14 on temperature platform 16 which are spaced proportionally to the temperature differential. This technique mechanically corrects the effective heat conduction area of a chip 12 considering its location on wafer 10. Those chips 12 near the center of wafer 10 have more grooves 14 underneath and thus less effective thermal conduction. Peripheral chips 12 see fewer or no grooves 14 at all. The proportional surface grooving of platform 16 maintains the temperature of chips 12 uniform despite location variations. The same result is achieved by utilizing plastic material 20 of relatively poor thermal conductivity at the center of platform 16 immediately beneath wafer 10. Material 20 is thickest at the center and tapers toward the periphery. By proper selection of material 20, the degree of taper and dimensions, uniform temperature of chips 12 at any location on the wafer can be maintained. Both techniques provide uniform temperature of chip wafers under test.

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