Browse Prior Art Database

Single Chip Carrier Package

IP.com Disclosure Number: IPCOM000090988D
Original Publication Date: 1969-Sep-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Carroll, A: AUTHOR [+4]

Abstract

A package for silicon chip 1 is constructed as shown. Copper cooling stud 2 is provided with a slit into which lead 3 fits. Stud 2 and lead 3 are brazed onto moly base 4. Frame 5 is bonded to base 4 with chip 1 protruding through the opening in frame 5. Chip 1 extends through the opening in frame 5 so as to be at the same level as the top surface of frame 5. KOVAR* lead frame 6 is placed on frame 5 so that the leads axially align with contact pads on chip 1. Frame 7 and top seal 8 are placed over frame 6 thus hermetically sealing chip 1 within the package. Seal 8 is sealed to frame 7 by a glass seal. Frame 6, stud 2, and base 4 are gold plated. Chip 1 is bonded to frame 6 by thermocompression bonding processes. *Trademark of Westinghouse Electric Corp.

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Single Chip Carrier Package

A package for silicon chip 1 is constructed as shown.

Copper cooling stud 2 is provided with a slit into which lead 3 fits.

Stud 2 and lead 3 are brazed onto moly base 4. Frame 5 is bonded to base 4 with chip 1 protruding through the opening in frame 5. Chip 1 extends through the opening in frame 5 so as to be at the same level as the top surface of frame 5. KOVAR* lead frame 6 is placed on frame 5 so that the leads axially align with contact pads on chip 1. Frame 7 and top seal 8 are placed over frame 6 thus hermetically sealing chip 1 within the package. Seal 8 is sealed to frame 7 by a glass seal. Frame 6, stud 2, and base 4 are gold plated. Chip 1 is bonded to frame 6 by thermocompression bonding processes. *Trademark of Westinghouse Electric Corp.

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