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Ovonic Memory

IP.com Disclosure Number: IPCOM000091020D
Original Publication Date: 1969-Sep-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Gamblin, RL: AUTHOR

Abstract

Junctionless semiconductor devices, termed ovonic memory switches, can be assembled and arranged in a coordinate type matrix to form an ovonic memory. The ovonic memory switch is a bistable device which can exist in either of two stable states in the absence of external power. In one state, the device exhibits an impedance of greater than ten megohms so long as a threshold voltage of five volts is not exceeded. In the second stable state, the device exhibits an impedance of less than one kilohm. To switch from a high-impedance state to a low-impedance state, a voltage of five volts is supplied to break down the device for a few tenths of a microsecond. To switch from the low-impedance state to a high-impedance state, a relatively slow, high-current pulse is supplied to the device.

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Ovonic Memory

Junctionless semiconductor devices, termed ovonic memory switches, can be assembled and arranged in a coordinate type matrix to form an ovonic memory. The ovonic memory switch is a bistable device which can exist in either of two stable states in the absence of external power. In one state, the device exhibits an impedance of greater than ten megohms so long as a threshold voltage of five volts is not exceeded. In the second stable state, the device exhibits an impedance of less than one kilohm. To switch from a high- impedance state to a low-impedance state, a voltage of five volts is supplied to break down the device for a few tenths of a microsecond. To switch from the low-impedance state to a high-impedance state, a relatively slow, high-current pulse is supplied to the device.

The memory is comprised of a nonconducting substrate supporting horizontal word line strips overlapping vertical bit line strips with areas of intersection of the strips forming the switches. The section drawing, taken along the line A-A, shows the overlapping relationship of a word line strip with a bit line strip with a layer of ovonic material between them.

In operation, it is assumed that all devices are in the high-impedance state to represent zeros. To write information into the memory, a voltage pulse Vw is supplied on a particular word line. If a one is to be written into a particular switch, an appropriate sense line is maintained at zero potential. On the other...