Browse Prior Art Database

Skew Corrector

IP.com Disclosure Number: IPCOM000091027D
Original Publication Date: 1969-Sep-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Mandra, RR: AUTHOR

Abstract

The system eliminates skew in data simultaneously read from two recording tracks which, for example, can be on opposite surfaces of a rotating disk not shown. First track circuit 14 senses the first bit in a record from either track. If the first sensed bit is from input track 1, outputs 14a and 14b respectively cause switching circuits 10 and 13 to select paths 10a and 10b, and 13a and 13b. However, if the first sensed bit is in input track 2, paths 10c and 10d, and 13c and 13d are selected. Thus, the lagging input track is connected to line 12 which passes it without delay to the output from circuits 13. The leading input track is connected to the input of sequential buffer 11 which delays the data by the amount of skew between the two tracks.

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Skew Corrector

The system eliminates skew in data simultaneously read from two recording tracks which, for example, can be on opposite surfaces of a rotating disk not shown. First track circuit 14 senses the first bit in a record from either track. If the first sensed bit is from input track 1, outputs 14a and 14b respectively cause switching circuits 10 and 13 to select paths 10a and 10b, and 13a and 13b. However, if the first sensed bit is in input track 2, paths 10c and 10d, and 13c and 13d are selected. Thus, the lagging input track is connected to line 12 which passes it without delay to the output from circuits 13. The leading input track is connected to the input of sequential buffer 11 which delays the data by the amount of skew between the two tracks. The amount of this skew delay is signalled by buffer delay controlling circuit 15 in response to output 14c from circuit 14. Relay 15 receives a signal from circuit 14 indicating the number of bits in the leading track occurring before the bit of the lagging track. This is provided as a signal to buffer 11 to indicate the amount of delay controlled within buffer 11. Thus, the leading track is delayed by an amount in buffer 11 so that the first bits in both track outputs are provided from circuits 13 at the same time that the first bit of the lagging track is provided to line 12. In this way two data streams are deskewed by buffering only the leading one of the two streams. This technique can be used to desk...