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IP.com Disclosure Number: IPCOM000091049D
Original Publication Date: 1969-Sep-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Maholick, AW: AUTHOR [+2]

Abstract

This circuit sorts a group of eight data words into a predetermined order. The eight data words are initially loaded in any order into eight registers 10 numbered 1...8. When the sort command is entered, clock 11 sends out four cycles of eight pulses. During T1 time, the magnitude of pairs of data words or of their priority designations, if any, are compared in compare circuits 12 to determine if the data of an odd-numbered register is greater than that of the next higher even-numbered register. If the data in the odd-numbered register is greater, at T2 time the data in the both registers is gated into interchange unit 13 under control of compare unit 12. At T4 time, each of the two data words is gated out to the other register 10 of the pair.

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Sorting Network

This circuit sorts a group of eight data words into a predetermined order. The eight data words are initially loaded in any order into eight registers 10 numbered 1...8. When the sort command is entered, clock 11 sends out four cycles of eight pulses. During T1 time, the magnitude of pairs of data words or of their priority designations, if any, are compared in compare circuits 12 to determine if the data of an odd-numbered register is greater than that of the next higher even-numbered register. If the data in the odd-numbered register is greater, at T2 time the data in the both registers is gated into interchange unit 13 under control of compare unit 12. At T4 time, each of the two data words is gated out to the other register 10 of the pair. At T5 time, the data then in each odd register, except the first, is compared in circuits 12 with the data in the next lower even-numbered register 10 to determine if that of the even-numbered register is larger than that of the odd-numbered register to its right. If the odd- number register data is lower, the data in the compared registers is again gated through interchange unit 13 to interchange the data so that the larger factor is in the right odd-numbered register 10. Three more repetitions of this cycle result in the shifting or nonshifting of the data words so that the words are stored in registers 10 in order of magnitude with the highest term in register 8.

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