Browse Prior Art Database

Address Decoder

IP.com Disclosure Number: IPCOM000091060D
Original Publication Date: 1969-Sep-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Schuenemann, CH: AUTHOR

Abstract

Integrated monolithic memories use address decoders on the same chip to overcome the restriction of pad terminals of semiconductor chips. In order to minimize power dissipation on the chip, it is desirable for the dissipation of word or bit line decoders to be decreased. Maximum power reduction in decoders is realized by a decoder comprising only one current path at any single time, with the remaining paths being dead.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Address Decoder

Integrated monolithic memories use address decoders on the same chip to overcome the restriction of pad terminals of semiconductor chips. In order to minimize power dissipation on the chip, it is desirable for the dissipation of word or bit line decoders to be decreased. Maximum power reduction in decoders is realized by a decoder comprising only one current path at any single time, with the remaining paths being dead.

The left drawing shows a decoder including switches S, connected to logic inputs lines by which such switches are set to either of two states. Current I, introduced at the top terminal is fed on either output line at the lower end, depending upon the condition of set lines A, A. A current path, conditioning the ABC output terminal Y4, is shown to provide a 1-out-of-8 decoding, i.e., to energize one line of Y1...Y8.

The three right drawings show different switches using monolithic techniques. These switches are represented by different storage cells or flip-flops comprising either two directly cross-coupled NPN transistors with ohmic load elements S1 or SCR cross-coupled memory cells S2 and S3. Such an address decoder has the advantage of substantial power dissipation occurring only during the setting time ts of the flip-flops. For the rest of the cycle time T-ts, e.g., 1 mus-50ns, only one current path with negligible dissipation is maintained.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]