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Parallel Adder using Functional Memories

IP.com Disclosure Number: IPCOM000091066D
Original Publication Date: 1969-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Schmookler, MS: AUTHOR

Abstract

Addition of two full 32-bit words is performed in a functional memory. Three associative memory cycles arc required to accomplish the addition.

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Parallel Adder using Functional Memories

Addition of two full 32-bit words is performed in a functional memory. Three associative memory cycles arc required to accomplish the addition.

The adder is formed of eight groups. Each group receives four information bits A and B. Input/output registers D1...D8 receive the operands initially and between each cycling stage of the memory. The memory tables for each group in each cycle are sixteen bits wide. The tables used in the groups for the first and third cycles are independent. The tables used in the second cycle are used together to form one table sixty-four bits wide. The tables used during the first cycle are nineteen words in length and the other tables are each forty-four words in length.

In the first memory cycle, the carry generates and carry propagates from each group are formed. Additionally, some internal propagates are formed for later use in the addition process. In the second memory cycle, the group carries are formed. In the third cycle, the final sums are produced using the original operand bits, the group carries and the internal propagates which are formed in the first cycle. In forming the sums, each group utilizes the carry-out of the group as well as the carry-in to the group. This reduces the number of words required in the table.

The memory cells employed are of the three state-type. Thus the indication in the tables is for a don't care condition.

This adder can be arranged so that internal group...